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| CYONS2000 OvationONSTM II Wired Laser Navigation System-on-Chip Features Description The CYONS2000 is a member of Cypress Semiconductor's second generation laser navigation system-on-chip (SoC) family of products. Powered by the high speed and high precision OptiCheckTM technology, along with the world leading PSoC technology, this family integrates the sensor, USB, and MCU functions into one chip. Bundled with the VCSEL into one package, the combination forms the market's first true mouse-on-a-chip solution. The CYONS2000 is the version that is designed for general purpose wired mouse applications. Enabled by the Cypress 0.13-micron mixed signal process technology, the device integrates the OptiCheck sensor with full-speed USB into a single silicon chip that enables seamless communication between sensor and MCU/full-speed USB. The sensor provides the best translation of precise hand motion into cursor motion on the PC. This highly integrated solution is programmable. It provides mouse suppliers the ease of use to design a single PCB system and customize their product. With the VCSEL integrated in the same package, designers do not need to calibrate the laser power during the manufacturing process. This greatly increases production throughput and reduces manufacturing costs. The innovative OvationONSTM II technology provides high precision, high speed motion tracking, and low power consumption. Designers can select from a family of integration options, ranging from low power to high performance, to target different types of wired and wireless design applications. The CYONS2000 solutions have a small form factor. Along with the lens, each package forms a complete and compact laser tracking system. This datasheet describes the detailed technology capabilities of the CYONS2000. Figure 1. CYONS2000/CYONSLENS2000 (2-Piece System) Programmable blocks (R) Highly integrated mouse-on-a-chip with PSoC microcontroller unit (MCU) 16 KB flash memory 2 KB static RAM (SRAM) Internal 24-, 12-, or 6-MHz main oscillator (IMO) Internal 32-kHz low-speed oscillator (ILO) 16-bit data report enables simultaneous high-speed and high-resolution tracking Tracking performance Selectable resolution of 400, 800, or 1600 counts per inch (CPI), independent of speed High speed with high accuracy tracking Speed up to 30 inches per second (in/s) Acceleration up to 20 g Peripheral interface Integrated full-speed USB for wired applications SPI master for interface to external functions 2 Fast or standard mode I C 28 general-purpose input/output (GPIO) pins Port 0 - 8 bits Port 1 - 8 bits with high current capability, regulated output voltage, and 5 V input tolerance Port 2 - 8 bits Port 3 - 4 bits Power Internal power system enables operation from a 5-V USB or 2.7 to 3.6 V external supply Self-adjusting power saving modes On-chip laser Vertical cavity surface emitting laser (VCSEL) integrated within the sensor package No calibration or alignment needed Electrostatic discharge (ESD) immunity: 2000 V (human body model) Wavelength: 840 to 870 nm IEC 60825-1 Class 1 Safety: built-in eye-safe fault tolerant laser drive circuitry Snap-on lens Molded optic: Self aligning snap on molded lens 6 mm distance between the printed circuit board (PCB) and tracking surface Cypress Semiconductor Corporation Document Number: 001-44044 Rev. *G * 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised January 3, 2011 [+] Feedback CYONS2000 Contents OvationONS II Family Performance Table...................... 3 OvationONS II Family Applications ................................ 3 OvationONS II Family Functional Description ............... 3 Pin Description ................................................................. 5 Microcontroller System.................................................... 7 Features ...................................................................... 7 PSoC Functional Overview.............................................. 8 The PSoC Core ........................................................... 8 The Analog Multiplexer System................................... 8 Additional System Resources ..................................... 8 Getting Started.................................................................. 8 Application Notes ........................................................ 8 Development Kits ........................................................ 8 Training ....................................................................... 8 CYPros Consultants .................................................... 8 Solutions Library.......................................................... 8 Technical Support ....................................................... 8 Development Tools .......................................................... 9 PSoC Designer Software Subsystems........................ 9 Designing with PSoC Designer ..................................... 10 Select User Modules ................................................. 10 Configure User Modules............................................ 10 Organize and Connect .............................................. 10 Generate, Verify, and Debug..................................... 10 Power Supply Connections ........................................... 11 Overview ................................................................... 11 Understanding DVDD................................................ 11 AVDD, VREGA, and VREGD .................................... 11 Using USB Power...................................................... 11 Using External Power................................................ 11 Filtering and Grounding............................................. 11 Wired Mouse Application Example............................... 12 Electrical Specifications ................................................ 13 Absolute Maximum Ratings....................................... 13 Operating Conditions................................................. 13 Power Consumption .................................................. 14 Power Specifications ................................................. 15 DC General Purpose I/O Specifications .................... 16 DC Analog Mux Bus Specifications........................... 17 DC Low Power Comparator Specifications ............... 17 DC POR and LVD Specifications .............................. DC Programming Specifications ............................... DC Characteristics - USB Interface........................... AC Chip Level Specifications .................................... AC General Purpose I/OI/O Specifications ............... AC External Clock Specifications .............................. AC Analog Mux Bus Specifications ........................... AC Programming Specifications................................ AC SPI Specifications ............................................... AC Comparator Specifications .................................. AC I2C Specifications................................................ AC USB Specifications.............................................. PCB Land Pads and Keepout Zones ........................ Orientation of Axes.................................................... PCB Mounting Height and Thickness........................ Thermal Impedances ................................................ Solder Reflow Peak Temperature ............................. Laser Safety Considerations ......................................... Laser Output Power .................................................. Laser Output Power Test Procedure......................... Registration Assistance............................................. Development Tool Selection ......................................... Software .................................................................... Mouse Design Kits .................................................... Development Kits ...................................................... Evaluation Tools........................................................ Device Programmers................................................. Third Party Tools ....................................................... Package Diagrams.......................................................... Ordering Information...................................................... Ordering Code Definition........................................... Document Conventions ................................................. Acronyms Used ......................................................... Units of Measure ....................................................... Numeric Naming........................................................ Document History Page ................................................. Sales, Solutions, and Legal Information ...................... Worldwide Sales and Design Support....................... Products .................................................................... PSoC Solutions ......................................................... 17 18 18 19 19 20 20 20 21 24 24 25 26 27 27 28 28 29 29 29 29 30 30 30 30 30 31 31 32 34 34 35 35 35 35 36 36 36 36 36 Document Number: 001-44044 Rev. *G Page 2 of 36 [+] Feedback CYONS2000 OvationONS II Family Performance Table Parameter Variable resolution Maximum speed Maximum acceleration Integrated MCU CapSense(R) Flash SRAM Interfaces CYONS2000 30 20 Yes No 16 2 CYONS2001 30 20 Yes No 16 2 CYONS2100 400-3200 75 30 Yes No 32 2 CYONS2101 400-3200 75 30 Yes No 32 2 CYONS2110 400-3200 75 30 Yes 26 inputs 32 2 KB KB Unit CPI in/s g 400, 800, 1600 400, 800, 1600 Full-speed USB 4-wire SPI Full-speed USB 4-wire SPI Full-speed USB 4-wire SPI up to 28 GPIOs 4-wire SPI up to 28 GPIOs 4 wire SPI up to 28 GPIOs up to 28 GPIO up to 28 GPIOs NA 4.25 to 5.25 2.7 to 3.6 1 0.8 to 3.6 NA 2.7 to 3.6 1 NA 4.25 to 5.25 2.7 to 3.6 1 0.8 to 3.6 NA 2.7 to 3.6 1 0.8 to 3.6 4.25 to 5.25 2.7 to 3.6 1 V V V count Battery supply voltage USB supply voltage External supply voltage Zero motion OvationONS II Family Applications Wired and wireless laser mice Gaming, graphic design, desktop, and mobile mice Optical trackballs Battery powered devices Motion sensing applications In addition to controlling the navigation engine, the PSoC MCU also serves as the main application processor. Based on Cypress's M8C architecture, the PSoC supports a rich instruction set, multiple processor speeds, and flexible GPIOs. Its internal main oscillator requires no external crystal. On-chip flash and RAM allow entire navigation systems to be implemented with the single SoC. The OvationONS II family supports a wide range of powering options. Internal regulators minimize the need for external circuitry. Depending on the product selected, the device can be power from a USB 5 V supply, from a single battery, from dual batteries, or from an external supply. The configuration and use of the power blocks are controlled with the integrated PSoC. Wired sensors include an integrated full-speed USB. As with the navigation engine and power system, the USB block is controlled by the integrated PSoC. All sensors support a 4-wire SPI interface. A typical use of the SPI interface is to provide access to a radio for wireless applications. An I2C interface is also included with all devices. The CYONS2110 device also supports CapSense functions, allowing additional features and differentiation in end products. All features of the OvationONS II family are configured using Cypress's PSoC DesignerTM software, allowing fast application development and time to market. The OvationONS II family block diagram is shown on Figure 2 on page 4. It shows a true SoC solution that enables design cycle reductions along with savings on manufacturing, PCB area, and component inventory management. The packaged solution delivers a fully integrated system that demonstrates tracking performance with efficient power consumption. OvationONS II Family Functional Description The OvationONS II family is a two-piece laser navigation SoC kit containing the integrated IC package and the molded lens. The 2 kV ESD rated IC package integrates the VCSEL and laser sensor SoC. Depending on the product selected, the SoC includes an MCU, flash, SRAM, two internal oscillators, CapSense system, battery boost regulator, power regulator, and full-speed USB. The molded lens collimates the VCSEL beam and images the light scattered from the tracking surface onto the sensor portion of the laser detector. The lens has features for registration to the package and easily snaps to the PC board. At the heart of the system is the OptiCheck laser navigation engine. It supports all functions required for tracking, including laser power control, resolution control, and self-adjusting power reduction, which reduces power consumption when motion stops. The laser output power is pre-calibrated to meet the eye safety requirements of IEC 60825 Class 1. The navigation engine is accessed and controlled by an integrated PSoC-based MCU. The interface between the two blocks is through a system bus and a collection of navigation engine interrupts. Full details are available in the OvationONS II Laser Navigation System-on-Chip TRM (Technical Reference Manual) or in the PSoC Designer integrated development environment (IDE) software. Document Number: 001-44044 Rev. *G Page 3 of 36 [+] Feedback CYONS2000 Figure 2. Block Diagram OptiCheckTM Navigation System VCSEL Laser Control DSP Resolution Control POWER BUS Ovation II Power System 3.3V Regulator Boost Regulator Power Control f Battery Filter Port 3 Port 2 Port 1 Port 0 1.8V Analog Regulator PSoC Core Regulator PSoC CORE SYSTEM BUS Global Analog Interconnect SRAM Interrupt Controller Supervisory ROM (SROM) Flash Nonvolatile Memory Sleep and Watchdog CPU Core (M8C) 6/12/24 MHz Internal Main Oscillator (IMO) Multiple Clock Sources 32 kHz Internal Low Speed Oscillator (ILO) SYSTEM BUS Full Speed USB Internal Voltage References System Resets POR and LVD SPI Master/ Slave Three 16-Bit Programmable Timers Digital Clocks I2C Slave ADC CapSense System SYSTEM RESOURCES NOTE: Shaded blocks indicate optional functions - Refer to OvationONSTM II Family Performance Table for details Document Number: 001-44044 Rev. *G Page 4 of 36 [+] Feedback CYONS2000 Pin Description This section describes, lists, and illustrates the CYONS2000 device pins and pinout configurations. The CYONS2000 is available in a 42-pin quad flat no-leads (QFN) package. Table 1. CYONS2000 Pin Description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 XRES DVSS DNU DVSS DVDD VREGD AVDD VREGA P2[7] P1[5] P1[3] P2[3] P2[5] P1[7] P1[1] P3[3] P1[0] P3[5] P1[6] P1[2] P2[2] P3[7] P3[1] OCDE AVSS P2[1] P2[0] P1[4] P2[4] DVSS P2[6] P0[0] P0[2] P0[4] P0[6] P0[1] Power Power Power Power Power I/O IOHR IOHR I/O I/O IOHR IOHR IOHR I/O I/O IOHR IOHR I/O I/O I/O OCD Power I/O I/O IOHR I/O Power I/O I/O I/O I/O I/O I/O Power Power Power Power Power I I I I I I I I I I I I I I I OCD Power I I I I Power I I I I I I Name Digital I Power Power Analog Digital ground Do not use Digital ground Digital supply voltage and regulated output (see Power Supply Connections on page 11) Digital VREG Analog supply voltage Analog VREG GPIO port 2 pin 7 SPI MISO, I2C_SDA, GPIO port 1 pin 5 SPI CLK, GPIO port 1 pin 3 GPIO port 2 pin 3 GPIO port 2 pin 5 SPI SS, I2C_SCL, GPIO port 1 pin 7 SPI MOSI, ISSP CLK[1], I2C_SCL, GPIO port 1 pin 1 HCLK (OCD high speed clock output), GPIO port 3 pin 3 ISSP DATA[1], I2C_SDA, GPIO port 1 pin 0 CCLK (OCD CPU clock output), GPIO port 3 pin 5 GPIO port 1 pin 6 GPIO port 1 pin 2 GPIO port 2 pin 2 OCDOE (OCD mode direction pin), GPIO port 3 pin 7 OCDO (OCD odd data output), GPIO port 3 pin 1 OCDE (OCD even data output) Analog ground GPIO port 2 pin 1 GPIO port 2 pin 0 EXT CLK, GPIO port 1 pin 4 GPIO port 2 pin 4 Digital ground GPIO port 2 pin 6 GPIO port 0 pin 0 GPIO port 0 pin 2 GPIO port 0 pin 4 GPIO port 0 pin 6 GPIO port 0 pin 1 Description Active high external reset with internal pull-down Document Number: 001-44044 Rev. *G Page 5 of 36 [+] Feedback CYONS2000 Table 1. CYONS2000 Pin Description (continued) Pin 37 38 39 40 41 42 CP P0[3] P0[5] P0[7] DD+ VDD5V DVSS Name Digital I/O I/O I/O I/O I/O Power Power Power Power Analog I I I GPIO port 0 pin 3 GPIO port 0 pin 5 GPIO port 0 pin 7 USB data USB data 5-V power Center pad (CP) must be connected to digital ground Description Legend: I=Input; O=Output; H=5 mA High Output Drive, R=Regulated Output, OCD = On-Chip-Debug Figure 3. Pin Diagram VDD5V D+ DAI, P0[7] AI, P0[5] AI, P0[3] AI, P0[1] AI, P0[6] 38 37 36 35 XRES DVSS DNU DVSS DVDD VREGD AVDD VREGA AI, P2[7] 1 2 3 4 5 6 7 8 9 42 41 40 39 34 33 32 31 30 29 28 27 26 25 24 23 AI, P0[4] AI, P0[2] AI, P0[0] AI, P2[6] DVSS AI, P2[4] AI, EXT CLK, P1[4] AI, P2[0] AI, P2[1] AVSS OCDE AI, OCDO, P3[1] CYONS2000 QFN (Top View) Note 1. These are the in-system serial programming (ISSP) pins. Unlike other GPIOs, they are not high impedance at power on reset (POR). See the Technical Reference Manual (TRM) or in the PSoC Designer development software for more details. Document Number: 001-44044 Rev. *G AI, SPI MISO, P1[5] AI, SPI CLK, P1[3] AI, P2[3] AI, P2[5] AI, SPI SS, P1[7] AI, SPI MOSI, ISSP CLK, P1[1] AI, HCLK, P3[3] AI, ISSP DATA, P1[0] AI, CCLK, P3[5] AI, P1[6] AI, P1[2] AI, P2[2] AI, OCDOE, P3[7] 10 11 12 13 14 15 16 17 18 19 20 21 22 Page 6 of 36 [+] Feedback CYONS2000 Microcontroller System Features Powerful Harvard-architecture processor M8C processor speed up to 24 MHz Low power at high speed Interrupt controller Operating temperature range: +5 C to +45 C Flexible on-chip memory 16 KB flash program storage 50,000 erase and write cycles 2 KB SRAM data storage Partial flash updates Flexible protection modes In-system serial programming (ISSP) Full-speed USB (12 Mbps) Eight unidirectional endpoints One bidirectional control endpoint USB 2.0 compliant Dedicated 512-byte buffer Internal 3.3-V output regulator Complete development tools Free development tool (PSoC Designer) Full featured in-circuit emulator (ICE) and programmer Full speed emulation Complex breakpoint structure 128 KB trace memory Precision programmable clocking Internal 5.0% 6-,12-, 24-MHz main oscillator Internal 32-kHz low speed oscillator Supports optional external 32-kHz crystal 0.25% accuracy for USB with no external crystal Programmable pin configurations 25-mA sink current on all GPIOs Pull-up, high-Z, open drain, or strong drive modes on all GPIOs Up to 28 analog inputs on GPIO Configurable inputs on all GPIOs Selectable, regulated digital I/O on port 1 * 3.3-, 2.5-, or 1.8-V output 3.0 V, 20 mA total port 1 source current 5-mA source current mode on ports 0 and 1 Hot swap capable Versatile analog mux Common internal analog bus Simultaneous connection of I/O combinations High power supply rejection ratio (PSRR) comparator Low dropout voltage regulator for the analog array Additional system resources SPI master and SPI slave * Clock speed up to 12 MHz Three 16-bit timers Watchdog and sleep timers Internal voltage reference Integrated supervisory circuit Analog-to-digital converter (ADC) 2 I C slave Document Number: 001-44044 Rev. *G Page 7 of 36 [+] Feedback CYONS2000 PSoC Functional Overview Cypress's PSoC on-chip controllers combine dynamic, configurable analog and digital blocks and an 8-bit MCU on a single chip, replacing multiple discrete components while delivering optimal flexibility and advanced functionality. A PSoC device includes configurable analog and digital blocks, and programmable interconnect. This architecture enables the creation of customized peripheral configurations, to match the requirements of each individual application. Additionally, a fast CPU, Flash program memory, SRAM data memory, and configurable I/O are included in a range of convenient pinouts. The architecture for this device family, as illustrated in the Block Diagram on page 4, contains: the core, the navigation sensor, the power system, and the system resources (including a full-speed USB port). A common, versatile bus enables connection between I/O and the analog system. GPIO is also included. The GPIO provides access to the MCU and analog mux. Getting Started For in depth information, along with detailed programming details, see the PSoC(R) Technical Reference Manual. For up-to-date ordering, packaging, and electrical specification information, see the latest PSoC device datasheets on the web. Application Notes Cypress application notes are an excellent introduction to the wide variety of possible PSoC designs. Development Kits PSoC Development Kits are available online from and through a growing number of regional and global distributors, which include Arrow, Avnet, Digi-Key, Farnell, Future Electronics, and Newark. Training Free PSoC technical training (on demand, webinars, and workshops), which is available online via www.cypress.com, covers a wide variety of topics and skill levels to assist you in your designs. The PSoC Core The PSoC core is a powerful engine that supports a rich instruction set. The PSoC core encompasses SRAM for data storage, an interrupt controller, sleep and watchdog timers, an Internal Main Oscillator (IMO), and an Internal Low Speed Oscillator (ILO). The CPU core, called the M8C, is a powerful processor with speeds up to 24 MHz. The M8C is a 4 MIPS, 8-bit Harvard architecture microprocessor. System resources provide additional capability, such as configurable USB and SPI master-slave communication interface, three 16-bit programmable timers, and various system resets supported by the M8C. CYPros Consultants Certified PSoC Consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC Consultant go to the CYPros Consultants web site. Solutions Library Visit our growing library of solution focused designs. Here you can find various application designs that include firmware and hardware design files that enable you to complete your designs quickly. The Analog Multiplexer System The analog mux bus connects to every GPIO pin. Pins are connected to the bus individually or in any combination. Analog signals may be routed to an internal analog-to-digital converter. Other multiplexer applications include: Technical Support Technical support - including a searchable Knowledge Base articles and technical forums - is also available online. If you cannot find an answer to your question, call our Technical Support hotline at 1-800-541-4736. Chip-wide mux that enables analog input from any I/O pin Crosspoint connection between any I/O pin combinations Additional System Resources System resources, some previously listed, provide additional capability useful to complete systems. Additional resources include low-voltage detection (LVD) and power on reset. Brief statements describing the merits of each system resource follow: The SPI master/slave module Provides communication over three or four wires Runs at speeds of 46.9 kHz to 3 MHz (lower for a slower system clock). An I2C slave module Low voltage detection (LVD) interrupts can signal the application of falling voltage levels, while the advanced Power On Reset (POR) circuit eliminates the need for a system supervisor. An internal reference provides an absolute reference for capacitive sensing. Page 8 of 36 Document Number: 001-44044 Rev. *G [+] Feedback CYONS2000 Development Tools PSoC DesignerTM is the revolutionary Integrated Design Environment (IDE) that you can use to customize PSoC to meet your specific application requirements. PSoC Designer software accelerates system design and time to market. Develop your applications using a library of precharacterized analog and digital peripherals (called user modules) in a drag-and-drop design environment. Then, customize your design by leveraging the dynamically generated application programming interface (API) libraries of code. Finally, debug and test your designs with the integrated debug environment, including in-circuit emulation and standard software debug features. PSoC Designer includes: Code Generation Tools The code generation tools work seamlessly within the PSoC Designer interface and have been tested with a full range of debugging tools. You can develop your design in C, assembly, or a combination of the two. Assemblers. The assemblers allow you to merge assembly code seamlessly with C code. Link libraries automatically use absolute addressing or are compiled in relative mode, and linked with other software modules to get absolute addressing. C Language Compilers. C language compilers are available that support the PSoC family of devices. The products allow you to create complete C programs for the PSoC family devices. The optimizing C compilers provide all of the features of C, tailored to the PSoC architecture. They come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. Debugger PSoC Designer has a debug environment that provides hardware in-circuit emulation, allowing you to test the program in a physical system while providing an internal view of the PSoC device. Debugger commands allow you to read and program and read and write data memory, and read and write I/O registers. You can read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The debugger also allows you to create a trace buffer of registers and memory locations of interest. Online Help System The online help system displays online, context-sensitive help. Designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer. In-Circuit Emulator A low-cost, high-functionality In-Circuit Emulator (ICE) is available for development support. This hardware can program single devices. The emulator consists of a base unit that connects to the PC using a USB port. The base unit is universal and operates with all PSoC devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the PSoC device in the target board and performs full-speed (24-MHz) operation. Application editor graphical user interface (GUI) for device and user module configuration and dynamic reconfiguration Extensive user module catalog Integrated source-code editor (C and assembly) Free C compiler with no size restrictions or time limits Built-in debugger In-circuit emulation Built-in support for communication interfaces: 2 Hardware and software I C slaves and masters Full-speed USB 2.0 Up to four full-duplex universal asynchronous receiver/transmitters (UARTs), SPI master and slave, and wireless PSoC Designer supports the entire library of PSoC 1 devices and runs on Windows XP, Windows Vista, and Windows 7. PSoC Designer Software Subsystems Design Entry In the chip-level view, choose a base device to work with. Then select different onboard analog and digital components that use the PSoC blocks, which are called user modules. Examples of user modules are analog-to-digital converters (ADCs), digital-to-analog converters (DACs), amplifiers, and filters. Configure the user modules for your chosen application and connect them to each other and to the proper pins. Then generate your project. This prepopulates your project with APIs and libraries that you can use to program your application. The tool also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic reconfiguration makes it possible to change configurations at run time. In essence, this allows you to use more than 100 percent of PSoC's resources for a given application. Document Number: 001-44044 Rev. *G Page 9 of 36 [+] Feedback CYONS2000 Designing with PSoC Designer The development process for the PSoC(R) device differs from that of a traditional fixed function microprocessor. The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that pays dividends in managing specification change during development and by lowering inventory costs. These configurable resources, called PSoC Blocks, have the ability to implement a wide variety of user-selectable functions. The PSoC development process is summarized in four steps: 1. Select User Modules. 2. Configure user modules. 3. Organize and connect. 4. Generate, verify, and debug. Organize and Connect You build signal chains at the chip level by interconnecting user modules to each other and the I/O pins. You perform the selection, configuration, and routing so that you have complete control over all on-chip resources. Generate, Verify, and Debug When you are ready to test the hardware configuration or move on to developing code for the project, you perform the "Generate Configuration Files" step. This causes PSoC Designer to generate source code that automatically configures the device to your specification and provides the software for the system. The generated code provides application programming interfaces (APIs) with high-level functions to control and respond to hardware events at run time and interrupt service routines that you can adapt as needed. A complete code development environment allows you to develop and customize your applications in either C, assembly language, or both. The last step in the development process takes place inside PSoC Designer's debugger (access by clicking the Connect icon). PSoC Designer downloads the HEX image to the ICE where it runs at full speed. PSoC Designer debugging capabilities rival those of systems costing many times more. In addition to traditional single-step, run-to-breakpoint and watch-variable features, the debug interface provides a large trace buffer and allows you to define complex breakpoint events that include monitoring address and data bus values, memory locations and external signals. Select User Modules PSoC Designer provides a library of prebuilt, pretested hardware peripheral components called "user modules." User modules make selecting and implementing peripheral devices, both analog and digital, simple. Configure User Modules Each user module that you select establishes the basic register settings that implement the selected function. They also provide parameters and properties that allow you to tailor their precise configuration to your particular application. For example, a pulse width modulator (PWM) User Module configures one or more digital PSoC blocks, one for each 8 bits of resolution. The user module parameters permit you to establish the pulse width and duty cycle. Configure the parameters and properties to correspond to your chosen application. Enter values directly or by selecting values from drop-down menus. All the user modules are documented in datasheets that may be viewed directly in PSoC Designer or on the Cypress website. These user module datasheets explain the internal operation of the user module and provide performance specifications. Each datasheet describes the use of each user module parameter, and other information you may need to successfully implement your design. Document Number: 001-44044 Rev. *G Page 10 of 36 [+] Feedback CYONS2000 Power Supply Connections Figure 4. Power Connections Block Diagram CYONS2000 4.25 - 5.25 V VDD5V 42 External 3.3V Supply, 15 mA max 10 nH 10 uF 10 uF 3.3V Regulator DVDD AVDD 5 7 USB IO Regulator VREGD 6 VREGA 8 Digital GND Analog GND 1.8V Analog Regulator 1.8V PSoC Core Regulator 1.8V Digital Circuitry 3V Digital Circuitry 1.8V Analog Circuitry 3V Analog Circuitry AVSS 25 DVSS Digital GND Analog GND Analog GND Digital GND DVSS Digital GND Overview The CYONS2000 incorporates a powerful and flexible powering system. It can be powered from one of two sources: a 5-V supply (typically from the USB VBUS line) or an external 3.3-V supply. Additionally, the CYONS2000's internal regulators can supply current to external devices. This section describes the capabilities and usage of the power system. Refer to Figure 4 for a block diagram of the CYONS2000's power system. Using USB Power For most USB applications, the device is powered from the USB VBUS signal. In this case, the 5-V VBUS signal should be connected directly to the CYONS2000's VDD5V pin. Using External Power The CYONS2000 can also be powered from an external source. In this case, the external 3.3-V source should connect to DVDD, and the VDD5V pin should be left unconnected. Understanding DVDD DVDD is a unique pin because it serves as either an input or an output. When the device is powered from USB (using the 3.3-V regulator), DVDD acts as an output, providing a 3.3-V voltage that can be used to power AVDD, VREGD, VREGA, and external parts. When the device is powered from an external 3.3-V supply, DVDD acts as an input only. Filtering and Grounding For all designs, it is important to provide proper grounding, and proper isolation between the analog and digital power supplies. The analog and digital grounds should be isolated, except for a single connection point that is placed as close as possible to the device. On the supply side, an L-C filter should be placed between AVDD and DVDD, as shown in Figure 4. AVDD, VREGA, and VREGD As with DVDD, these signals power the internal circuitry of the device. Unlike DVDD, these are always inputs. They should be connected as shown in Figure 4. Document Number: 001-44044 Rev. *G DVSS 30 Digital GND 2 4 Page 11 of 36 [+] Feedback USB Interface VCC_5V AVCC VCC_5V DVCC DVCC 8 5 42 W G R B SHLD + U2 C4 1 2 3 4 5 7 6 10 uF AVDD DVDD VREGA VDD5V 1 nF 22 DPLUS 1M 22 1206 VREGD CP AVSS 43 25 AGND 30 AGND DVSS Document Number: 001-44044 Rev. *G Mouse Button Switches 1 2 LF_SW SW PUSHBUTTON Vbus D+/SDATA D-/SCLK GND 1 2 3 4 5 1 2 2 DP DM GND GND_SHIELD Wired Mouse Application Example RT_SW SW PUSHBUTTON BOOST_GND 1 BATT_MON 4 2 SW PUSHBUTTON CTR_SW DMINUS 1 22 18 16 24 23 XRES OCDOE, P3_7 CCLK, P3_5 HCLK, P3_3 OCDE OCDO, P3_1 S LF_SW RT_SW CTR_SW AVCC 10 nH 0.1 uF + 10 uF 10 uF + Z-WHEEL1 Z-WHEEL2 Sensor Decoupling Caps DVCC VCC Filter Z WHEEL Z-WHEEL1 Z-WHEEL2 2 3 QA QB COM GND1 GND2 ENCODER 1 4 5 AVCC DVCC VCC_5V 32 36 33 37 34 38 35 39 P0_0 P0_1 P0_2 P0_3 P0_4 P0_5 P0_6 P0_7 ISSP DATA, P1_0 SPI_MOSI, ISSP CLK, P1_1 P1_2 SPI_CLK, P1_3 EXT_CLK, P1_4 SPI MISO, P1_5 P1_6 SPI SS, P1_7 17 15 20 11 28 10 19 14 Figure 5. Wired Mouse 0.1 uF 0.1 uF CYONS2000 DD+ 40 41 DMINUS DPLUS AGND AGND Zero 27 26 21 12 29 13 31 9 P2_0 P2_1 P2_2 P2_3 P2_4 P2_5 P2_6 P2_7 CYONS2000 Figure 5 shows an implementation of a wired mouse. For complete details, refer to the CY4631 - OvationONSTM II Laser Gaming Mouse Reference Design Kit. Page 12 of 36 [+] Feedback CYONS2000 Electrical Specifications This section presents the DC and AC electrical specifications of the CYONS2000 device. For the most up-to-date electrical specifications, confirm that you have the most recent datasheet by visiting http://www.cypress.com. Absolute Maximum Ratings Parameter Storage temperature[2] Operating temperature Lead solder temperature Supply voltage, DVDD, AVDD, VREGA, and VREGD relative to DVSS) Supply voltage, VDD5V relative to DVSS Electrostatic discharge (ESD) I/O Voltage relative to DVSS I/O voltage relative to DVSS Latch up current Maximum current into any GPIO pin Min -40 -5 - - - - -0.5 - - -25 - - - - - - - - Typ 25 Max 65 55 260 3.6 5.5 2.0 DVDD + 0.5 5.5 100 +50 Unit C C C V V kV V V mA mA All pins, HBM MIL 883 method 3015 GPIO ports 0, 2, and 3 GPIO port 1 Conditions Case temperature Case temperature 10 seconds Operating Conditions Parameter Operating temperature Power supply voltage VDD5V DVDD, AVDD, VREGD VREGA Power supply rise time Supply noise - AVDD (sinusoidal) Supply noise - VDD, DVDD (sinusoidal) Distance from PCB to tracking surface PCB thickness Min 5 4.35 2.70 1.71 100 - - 5.80 1.54 Typ - - Max 45 5.25 3.60 3.60 - 25 100 6.20 1.79 Unit C V Conditions - - - 6 - s mV pp mV pp mm mm 10 kHz to 50 MHz 10 kHz to 50 MHz See Figure 15 on page 26 See Figure 15 on page 26 Note 2. High storage temperature reduces flash data retention time specified in Table 7 on page 18. Recommended storage temperature is 25 25 C. Extended duration above 65 C can degrade reliability. Document Number: 001-44044 Rev. *G Page 13 of 36 [+] Feedback CYONS2000 Power Consumption Introduction As described in Overview on page 11, the CYONS2000 has a highly advanced power system that can be used to develop very low-power applications. This section describes and specifies the power consumption performance of the device. Enabling Low Power Modes In some cases, designers may want to develop "always-on" applications, with no power-saving modes and consequently no wakeup latency in performance. In other applications, conserving power is crucial, and power saving modes are a firm requirement. The CYONS2000 enables low-power modes to be enabled or disabled in firmware, either through register writes or through the application programming interface in Cypress's PSoC Designer development software. The remainder of this section applies to applications requiring power saving modes. Operating Modes From a power consumption standpoint, consider these three operating modes: with four sets of sleep mode settings, enabling four levels of sleep. By controlling the parameters of these four sleep modes, the designer can tailor the solution to make appropriate tradeoffs between power consumption and wakeup latency. The transition between sleep modes is under the control of the CYONS2000's digital signal processor (DSP) - no firmware needs to be written to manage the transition between modes. Each of the four available sleep modes is defined by three parameters. These parameters are defined as registers that can be controlled by firmware, either through direct register writes or by using the NAV User Module in PSoC Designer. Sleep time: This is the amount of time that the device is in its low power inactive state. Motion threshold: This is the amount of motion that is required to bring the device out of sleep. Sleep mode time: This is the amount of time that the device stays in a particular sleep mode before transitioning to the next lowest sleep mode. Longer sleep times save power but have higher wakeup latency. Tracking mode: In this mode, the device is actively tracking on a surface. It is the highest power mode of the device. The current consumption has a slight dependence on speed and surface. The current, however, is independent of resolution. Inactive mode: In this mode, the device is in its lowest power state. In inactive mode, the device cannot sense motion, but a timer is running. This timer can generate an interrupt that can wake the rest of the device and start tracking motion. Sleep modes: In sleep modes, the device self-transitions between tracking mode and inactive mode. The typical use of sleep modes is when the device is at rest, but might still be moved. In Sleep modes, the CYONS2000 stays in inactive mode for a fixed time, then wakes up and checks for motion. If motion is detected, the device fully wakes up and begins tracking. If no motion is detected, the device can go back to Sleep mode. Figure 6 shows the flowchart for a particular sleep mode, showing how the three parameters affect behavior. Calculating Power for Sleep Mode The power consumption in sleep mode can be found by using a duty cycle calculation. The sleep mode current is determined by the tracking mode current, the inactive current, the time required to check for motion (typically 2.9 ms), and the time between check-for-motion events. The expected current consumption is given by the formula I TRACK x 2.9 + I INACT x T SLEEP I SLEEP = ---------------------------------------------------------------------------------2.9 + T SLEEP where ISLEEP is the sleep current, ITRACK is the tracking current, IINACT is the inactive current, and TSLEEP is the time (in ms) in the low power state. As an example, if the tracking current is 8.5 mA, the inactive current is 7.5 A and the sleep time is 100 ms, then the expected sleep current is 0.25 mA. Power Management Through Sleep Mode Control Power management for the CYONS2000 consists of setting the parameters that define the sleep modes. The device is equipped Figure 6. Sleep Mode Flowchart Enter from higher sleep mode Go to sleep for N ms Wake up, check for motion Motion > threshold T? N Y Go to active tracking mode Time in mode > M sec? N Y Go to deeper sleep mode Document Number: 001-44044 Rev. *G Page 14 of 36 [+] Feedback CYONS2000 Power Specifications There are two ways to power the CYONS2000 - external powering and USB powering. Table 4 provides the current consumption values for each mode. With external powering, a 3-V supply is connected to DVDD, AVDD, VREGD, and VREGA, and the internal regulator is turned off. In this case, the current consumption during tracking is ITRACK_EXT, and the consumption during sleep is ISLEEP. With USB powering, the 5-V USB supply is connected to VDD5V, and DVDD, AVDD, VREGD, and VREGA are driven by the internal regulator. Tracking current is specified by ITRACK_USB. Sleep current must include the current consumption of the regulator itself, and is specified by the sum of ISLEEP and IREG5V. Sleep current is achieved by activating "Navigation Sleep Table 2. Power Specifications Symbol Description Modes" in Cypress's PSoC Designer development environment. Doing so enables the sleep mode progressions described in Operating Modes on page 14. If sleep modes are not activated, the device current stays at tracking levels, even when the device is not sensing motion. ISB_EXT is the current in the lowest-power mode of the device. In this mode, the CPU is halted and operation can only be restarted with an external reset at the XRES pin. For designs using the CYONS2000, low-power operation is often only needed to support USB Suspend. The reference code for this is available in the CY4631 - OvationONSTM II Laser Gaming Mouse Reference Design Kit. Conditions Min - - Typ 9 12.5 Max 12.5 16 Units mA mA ITRACK_EXT Tracking current into DVDD, 3.0 V, 25 C, 5 in/s, 24-MHz IMO, 6-MHz CPU clock, AVDD, VREGD, VREGA white surface, nominal tracking height ITRACK_USB Tracking current into VDD5V 5.25 V, 25 C, 5 in/s, 24-MHz IMO, 6-MHz CPU clock, white surface, nominal tracking height, DVDD, AVDD, VREGD, and VREGA powered by internal regulator IINACT ISLEEP IREG5V ISB_EXT ISB_USB Inactive current into DVDD, AVDD, VREGD, VREGA Sleep current into DVDD, AVDD, VREGD, VREGA 5 V-to-3 V regulator current consumption 3.0 V, 25 C, CPU in sleep state 3.0 V, 25 C VDD5V = 5.25 V, regulator active - 7 14 A See Calculating Power for Sleep Mode on page 14 for equation - - 250 4 - 11 A A Shutdown current into DVDD, 3.0 V, 25 C, 5-V supply not present AVDD, VREGD, VREGA, all blocks off Shutdown current, all blocks 5.25 V, 25 C, DVDD, AVDD, VREGA, VREGD off, into VDD5V powered by internal 5-V-to-3-V regulator in standby mode - 80 - A Document Number: 001-44044 Rev. *G Page 15 of 36 [+] Feedback CYONS2000 DC General Purpose I/O Specifications GPIOs are arranged into four ports. Ports 0, 1, and 2 have eight GPIO pins and Port 3 has four GPIO pins. Port 1 has an optional low drop out (LDO) regulator that adjusts the port's output voltage to 1.8, 2.5, or 3.0 V. Additionally, each GPIO pin can be independently set to one of the four drive modes: strong drive, open drain, pull-up, or high-Z analog. Rise and fall times are specified for 10% and 90% voltage values. The following tables list guaranteed maximum and minimum specifications for the voltage range of 2.7 V to 3.6 V at the DVDD pin, and over the temperature range 5 C TA 45 C. Typical parameters apply to 3.3 V at 25 C and are for design guidance only. Table 3. 2.7 V to 3.6 V DC GPIO Specifications Symbol RPU VOH1 VOH2 VOH3 VOH4 VOH5 VOH6 VOH7 VOH8 VOH9 VOH10 VOL Description Pull-up resistor High output voltage Port 2 or 3 pins High output voltage Port 2 or 3 pins High output voltage Port 0 or 1 pins with LDO regulator disabled for Port 1 High output voltage Port 0 or 1 pins with LDO regulator disabled for Port 1 High output voltage Port 1 pins with LDO regulator enabled for 3 V Out High output voltage Port 1 pins with LDO regulator enabled for 3 V Out High output voltage Port 1 pins with LDO enabled for 2.5 V Out High output voltage Port 1 pins with LDO enabled for 2.5 V Out High output voltage Port 1 pins with LDO enabled for 1.8 V Out High output voltage Port 1 pins with LDO enabled for 1.8 V Out Low output voltage Conditions Pin configured for pull-up mode. IOH < 10 A, maximum of 10-mA source current in all I/Os. IOH = 1 mA, maximum of 20-mA source current in all I/Os. IOH < 10 A, maximum of 10-mA source current in all I/Os. IOH = 5 mA, maximum of 20-mA source current in all I/Os. IOH < 10 A, DVDD > 3.1 V, maximum of 4 I/Os all sourcing 5 mA. IOH = 5 mA, DVDD > 3.1 V, maximum of 20 mA source current in all I/Os. IOH < 10 A, DVDD > 2.7 V, maximum of 20 mA source current in all I/Os. IOH = 2 mA, DVDD > 2.7 V, maximum of 20 mA source current in all I/Os. IOH < 10 A, DVDD > 2.7 V, maximum of 20 mA source current in all I/Os. IOH = 1 mA, DVDD > 2.7 V, maximum of 20 mA source current in all I/Os. IOL = 25 mA, DVDD > 3.3 V, maximum of 60-mA sink current on even port pins (for example, P0[2] and P1[4]) and 60-mA sink current on odd port pins (for example, P0[3] and P1[5]). Min 4.0 DVDD - 0.2 DVDD - 0.9 DVDD - 0.2 Typ 5.6 - - - Max 8.0 - - - Units k V V V DVDD - 0.9 - - V 2.85 3.00 3.30 V 2.20 - - V 2.35 2.50 2.75 V 1.90 - - V 1.60 1.80 2.10 V 1.20 - - V - - 0.75 V VIL VIH VH IIL CPIN Input low voltage Input high voltage Input hysteresis voltage Input leakage (absolute value) Pin capacitance Gross tested to 1 A. Temp = 25 C. - 2.00 - - 0.5 - - 80 0.5 1.7 0.80 - 1.0 8.0 V V mV A pF Document Number: 001-44044 Rev. *G Page 16 of 36 [+] Feedback CYONS2000 DC Analog Mux Bus Specifications The analog mux bus can connect signals from GPIOs to and from internal analog blocks and other GPIOs. Table 4 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 4. DC Analog Mux Bus Specifications Parameter RSW RGND Description Switch resistance to common analog bus Resistance of initialization switch to DVSS Conditions Pin voltage < 1.8 V Pin voltage < 1.8 V Min - - Typ - - Max 800 800 Unit DC Low Power Comparator Specifications The device includes two general-purpose comparators, using internal or external signals from the analog mux bus. Table 5 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 5. DC Comparator Specifications Parameter VLPC ILPC VOSLPC Description Low power comparator (LPC) common mode LPC supply current LPC voltage offset Conditions Maximum voltage limited to DVDD. Min 0.0 - - Typ - 10 2.5 Max 1.8 40 30 Unit V A mV DC POR and LVD Specifications The device features two mechanisms for dealing with low power supply voltages. Both power-on reset (POR) and LVD events occur when DVDD falls below a threshold. A POR completely resets the device. An LVD generates an interrupt to the MCU, allowing the application developer to better manage power supply drops. The POR threshold is defined by bits 7 (HPOR) and 5:4 (PORLEV) and of the VLT_CR register at address E3h in register bank 1. The LVD threshold is defined by bits 2:0 (VM) of the same register. Refer to the technical reference manual for more details. The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 6. DC POR and LVD Specifications Parameter VPOR0 VPOR1 VPOR2 VPOR3 VLVD0 VLVD1 VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 Description DVDD Value for POR trip PORLEV[1:0] = 00b, HPOR = 0 PORLEV[1:0] = 00b, HPOR = 1 PORLEV[1:0] = 01b, HPOR = 1 PORLEV[1:0] = 10b, HPOR = 1 DVDD Value for LVD trip VM[2:0] = 000b VM[2:0] = 001b VM[2:0] = 010b VM[2:0] = 011b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b Conditions DVDD must be greater than or equal to 1.71 V during startup, reset from the XRES pin, or reset from watchdog. Min 1.61 - - - 2.40[3] 2.64[4] 2.85[5] 2.95 3.06 1.84 1.75[6] Typ 1.66 2.36 2.60 2.82 2.45 2.71 2.92 3.02 3.13 1.90 1.80 Max 1.71 2.40 2.65 2.95 2.51 2.78 2.99 3.09 3.20 1.96 1.84 Unit V V V V V V V V V V V Notes 3. Always greater than 50 mV above VPOR1 voltage for falling supply. 4. Always greater than 50 mV above VPOR2 voltage for falling supply. 5. Always greater than 50 mV above VPOR3 voltage for falling supply. 6. Always greater than 50 mV above VPOR0 voltage for falling supply. Document Number: 001-44044 Rev. *G Page 17 of 36 [+] Feedback CYONS2000 DC Programming Specifications Table 7 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. The CYONS2000 must be properly powered for flash programming, with DVDD, AVDD, VREGD, and VREGA all held within the specified range. A suitable option for in-circuit programming USB designs is to apply 5 V to the VDD5V pin and use the internal regulator to drive DVDD, AVDD, VREGD, and VREGA. This enables direct connection to Cypress's CY3210-Miniprog. For in-circuit programming of externally powered designs, the designer must include provisions for supplying DVDD, AVDD, VREGD, and VREGA externally. Table 7. DC Programming Specifications Parameter VIW IDDP VILP VIHP IILP IIHP VOLP VOHP Description Supply voltage for flash write operations Supply current during programming or verify Input low voltage during programming or verify Input high voltage during programming or verify See DC General Purpose I/O Specifications on page 16. See DC General Purpose I/O Specifications on page 16. Conditions VIW applied to DVDD, AVDD, VREGD, and VREGA Min 2.7 - - VIH - - - DC General Purpose I/O Specifications on page 16. For DVDD > 3 V use the value with IOH = 5 mA. Erase/write cycles by block. Following maximum flash write cycles at ambient temp of 45 C VOH Typ - 5 - - - - - - Max 3.6 25 VIL - 0.2 1.5 DVSS + 0.75 DVDD Unit V mA V V mA mA V V Input current when applying VILP to ISSP CLK and Driving internal pull-down resistor. ISSP DATA pins during programming or verify Input current when applying VIHP to ISSP CLK and Driving internal pull-down resistor. ISSP DATA pins during programming or verify Output low voltage during programming or verify Output high voltage during programming or verify FlashENPB FlashDR Flash write endurance Flash data retention 50,000 5 - 10 - - Cycles Years DC Characteristics - USB Interface The device includes an integrated full-speed USB block. Table 8 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 8. DC USB Characteristics Symbol Rusbi Rusba Vohusb Volusb Vdi Vcm Vse Cin Iio Rps2 Rext Description USB D+ pull-up resistance USB D+ pull-up resistance Static output high Static output low Differential input sensitivity Differential input common mode range Single-ended receiver threshold Transceiver capacitance High-Z state data line leakage PS/2 pull-up resistance External USB series resistor In series with each USB pin On D+ or D- line Conditions With idle bus While receiving traffic Min 0.900 1.425 2.8 - 0.2 0.8 0.8 - -10 3 21.78 Typ - - - - - - - - - 5 22 Max 1.575 3.090 3.6 0.3 - 2.5 2.0 50 +10 7 22.22 Units k k V V V V V pF uA k Document Number: 001-44044 Rev. *G Page 18 of 36 [+] Feedback CYONS2000 AC Chip Level Specifications The device has two internal oscillators. The IMO controls the clock speeds for the CPU. A programmable frequency divider allows the CPU to run at lower speeds than the IMO. The ILO is a typically active in sleep modes, clocking sleep, and watchdog timers. Other internal timers can be clocked by either the CPU clock or the ILO. Table 9 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 9. AC Chip Level Specifications Parameter FIMO24 FIMO12 FIMO6 DCIMO FCPU F32K1 TRAMP TXRST TXRST2 TMOT Description IMO frequency for 24-MHz setting IMO frequency for 12-MHz setting IMO frequency for 6-MHz setting IMO output duty cycle at 6 and 12-MHz setting CPU frequency[8] ILO frequency[9] Supply ramp time External reset pulse width at power-up External reset pulse width after power-up Motion delay from reset to valid tracking data[10] [7] Min 22.8 11.4 5.7 40 FIMO / 256 19 20 1 10 - Typ 24 12 6.0 50 - 32 - - - - Max 25.2 12.6 6.3 60 FIMO 50 - - - 30 Unit MHz MHz MHz % MHz kHz s ms s ms AC General Purpose I/OI/O Specifications GPIOs are arranged into four ports. Ports 0, 1, and 2 have eight GPIO pins and Port 3 has four GPIO pins. Port 1 has an optional LDO regulator that adjusts the port's output voltage to 1.8, 2.5, or 3.0 V. Additionally, each GPIO pin can be independently set to one of four drive modes: strong drive, open drain, pull-up, or high-Z analog. Rise and fall times are specified for 10% and 90% voltage values. Specifications are for the entire operating temperature range. Table 10. AC GPIO Specs Parameter FGPIO TRISE_01 TRISE_01_L TRISE_LDO_3 TRISE_LDO_2.5 TRISE_LDO_1.8 TRISE_23 TFALL TFALL_L TFALL_LDO_3 TFALL_LDO_2.5 TFALL_LDO_1.8 Description GPIO operating frequency Rise time, ports 0 -1 Rise time, ports 0 -1, low supply Strong drive Strong drive, CLOAD = 50 pF, DVDD = 3.0 - 3.6 Strong drive, CLOAD = 50 pF, DVDD = 2.7 - 3.0 Conditions Min 0 - - - - - - - - - - - Typ - - - - - - - - - - - - Max 12 50 70 50 70 100 80 50 70 50 70 80 Units MHz ns ns ns ns ns ns ns ns ns ns ns Rise time, port 1, 3 V LDO enabled Strong drive, CLOAD = 50 pF, DVDD > 3.1 V Rise time, port 1, 2.5 LDO enabled Strong drive, CLOAD = 50 pF, DVDD > 2.7 V Rise time, port 1, 1.8 LDO enabled Strong drive, CLOAD = 50 pF, DVDD > 2.7 V Rise time, ports 2 - 3 Fall time, all ports Fall time, all ports, low supply Strong drive, CLOAD = 50 pF, DVDD = 2.7 - 3.6 Strong drive, CLOAD = 50 pF, DVDD = 3.0 - 3.6 Strong drive, CLOAD = 50 pF, DVDD = 2.7 - 3.0 Fall time, port 1, 3 V LDO enabled Strong drive, CLOAD = 50 pF, DVDD > 3.1 V Fall time, port 1, 2.5 LDO enabled Strong drive, CLOAD = 50 pF, DVDD > 2.7 V Fall time, port 1, 1.8 LDO enabled Strong drive, CLOAD = 50 pF, DVDD > 2.7 V Notes 7. IMO can be output from chip by routing to GPIO. Maximum GPIO output frequency is 12 MHz, so duty cycle at 24 MHz is not defined. See Technical Reference Manual at www.cypress.com or in Cypress's PSoC Designer software for details on routing IMO to GPIO pin. 8. Available frequency divisors are 1, 2, 4, 8, 16, 32, 128, and 256. 9. 32 kHz oscillator can be locked to external crystal. See technical reference manual available at www.cypress.com or in Cypress' PSoC Designer software. 10. Value provided represents maximum startup time for typical application. Applications requiring additional startup code, processing, or delay may increase TMOT. Document Number: 001-44044 Rev. *G Page 19 of 36 [+] Feedback CYONS2000 AC External Clock Specifications The IMO can be replaced with an external clock at the EXT CLK / P[1]4 pin. Refer to the technical reference manual for more details. Table 11 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 11. AC External Clock Specifications Parameter FOSCEXT - - - Frequency High period Low period Required time to run from IMO before switching to external clock Description Min 0.750 20.6 20.6 150 Typ - - - - Max 25.2 5300 - - Unit MHz ns ns s AC Analog Mux Bus Specifications Table 12 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 12. AC Analog Mux Bus Specifications Parameter FSW Switch rate Description Conditions Pin voltage < 1.8 V Min - Typ - Max 6.3 Unit MHz AC Programming Specifications The analog mux bus can connect signals from GPIOs to and from internal analog blocks and other GPIOs. Table 13 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 13. AC Programming Specifications Symbol TRSCLK TFSCLK TSSCLK THSCLK FSCLK TERASEB TWRITE TDSCLK2 Description Rise time of ISSP CLK Fall time of ISSP CLK Data setup time to falling edge of ISSP CLK Data hold time from falling edge of ISSP CLK Frequency of ISSP CLK Flash erase time (Block) Flash block write time Data out delay from falling edge of ISSP CLK 3.0 DVDD 3.6 Conditions Min 1 1 40 40 0 - - - Typ - - - - - - - - Max 20 20 - - 8 18 25 85 Units ns ns ns ns MHz ms ms ns Document Number: 001-44044 Rev. *G Page 20 of 36 [+] Feedback CYONS2000 AC SPI Specifications Table 14 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 14. AC SPI Master Specifications Parameter fSCLK tSETUP tHOLD tOUT_SU tOUT_H SPI CLK frequency [11] Description SPI MISO to SPI CLK setup time SPI CLK to SPI MISO hold time SPI MOSI to SPI CLK setup time SPI CLK to SPI MOSI hold time Min - 60 40 40 40 Typ - - - - - Max FIMO/2 - - - - Unit MHz ns ns ns ns Table 15. AC SPI Slave Specifications Parameter fSCLK tLOW tHIGH tSETUP tHOLD tOUT_H tSS_MISO tSCLK_MISO tSS_HIGH tSS_CLK tCLK_SS SPI CLK frequency[11] Minimum SPI CLK low width[12] Minimum SPI CLK high width[12] SPI MOSI to SPI CLK setup time SPI CLK to SPI MOSI hold time SPI CLK to SPI MISO hold time SPI SS to SPI MISO valid SPI CLK to SPI MISO valid Minimum SPI SS high width Time from SPI SS low to first SPI CLK Time from last SPI CLK to SPI SS high Description Min - 41.67 41.67 25 25 35 - - - - - Typ - - - - - - - - - - - Max 12 - - - - - 100 140 35 20 25 Unit MHz ns ns ns ns ns ns ns ns ns ns Notes 11. Clock frequency is half of clock input to SPI block. 12. Value corresponds to 50% duty cycle at 12 MHz. Document Number: 001-44044 Rev. *G Page 21 of 36 [+] Feedback CYONS2000 Figure 7. SPI Master Timing Diagram, Modes 0 and 2 Figure 8. SPI Master Timing Diagram, Modes 1 and 3 Document Number: 001-44044 Rev. *G Page 22 of 36 [+] Feedback CYONS2000 Figure 9. SPI Slave Timing Diagram, Modes 0 and 2 Figure 10. SPI Slave Timing Diagram, Modes 1 and 3 Document Number: 001-44044 Rev. *G Page 23 of 36 [+] Feedback CYONS2000 AC Comparator Specifications The device includes two general-purpose comparators, using internal or external signals from the analog mux bus. Table 16 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 16. AC Low Power Comparator Specifications Symbol TLPC Description Comparator response time, 50 mV overdrive Conditions 50 mV overdrive does not include offset voltage Min - Typ - Max 100 Units ns AC I2C Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 17. AC Characteristics of the I2C SDA and SCL Pins Symbol FSCLI2C THDSTAI2C TLOWI2C THIGHI2C TSUSTAI2C THDDATI2C TSUDATI2C TBUFI2C TSPI2C I2C_SCL clock frequency Hold time for START and Repeated START condition LOW period of the I2C_SCL clock HIGH period of I2C_SCL clock Setup time for a START and Repeated START condition Data hold time Data setup time Bus free time between a STOP and START condition Pulse width of spikes that are suppressed by the input filter Description Standard Mode Min 0 4.0 4.7 4.0 4.7 0 250 4.0 4.7 - Max 100 - - - - - - - - - Fast Mode Min 0 0.6 1.3 0.6 0.6 0 100[13] 0.6 1.3 0 Max 400 - - - - - - - - 50 Units kHz s s s s s ns s s ns TSUSTOI2C Setup time for STOP condition Figure 11. Timing for Fast/Standard Mode on the I2C Bus I2C_SDA TSUDATI2C THDSTAI2C I2C_SCL TSPI2C THDDATI2CTSUSTAI2C TBUFI2C THIGHI2C TLOWI2C S START Condition Sr Repeated START Condition TSUSTOI2C P STOP Condition S Note 13. A Fast-Mode I2C-bus device can be used in a Standard Mode I2C-bus system, but the requirement tSUDATI2C 250 ns must then be met. This automatically is the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax + tSUDATI2C = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released. Document Number: 001-44044 Rev. *G Page 24 of 36 [+] Feedback CYONS2000 AC USB Specifications The device includes an integrated full-speed USB block. Table 18 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 18. AC Characteristics - USB Data Timing Specifications Symbol Tdrate Tdjr1 Tdjr2 Tudj1 Tudj2 Tfdeop Tfeopt Tfeopr Tfst Description Full speed data rate Receiver data jitter tolerance Receiver data jitter tolerance Driver differential jitter Driver differential jitter Source jitter for differential transition Source SE0 interval of EOP Receiver SE0 interval of EOP Width of SE0 interval during differential transition Conditions Average bit rate To next transition To pair transition To next transition To pair transition To SE0 transition Min 12-0.25% -18.5 -9 -3.5 -4.0 -2 160 82 - Typ 12 - - - - - - - - 14 Max 12 + 0.25 18.5 9 3.5 4.0 5 175 Units MHz ns ns ns ns ns ns ns ns Table 19. AC Characteristics - USB Driver Symbol Tr Tf TR Vcrs Description Transition rise time Transition fall time Rise/fall time matching Output signal crossover voltage 50 pF 50 pF 0.8 V to 2.5 V Conditions Min 4 4 90 1.3 Typ - - - - Max 20 20 111 2.0 Units ns ns % V Document Number: 001-44044 Rev. *G Page 25 of 36 [+] Feedback CYONS2000 PCB Land Pads and Keepout Zones Figure 12 and Figure 13 show the recommended land pad architecture and keepout zones. The pads on the 42-pin device are a subset of the JEDEC MO-220 52-pin QFN standard. For detailed layout instructions, see the application note AN48995, Mechanical Design Considerations for the OvationONSTM II Laser Navigation System-on-Chip. Figure 12. Land Pad Architecture and Spacing Figure 13. PCB Keep Out Zones Document Number: 001-44044 Rev. *G Page 26 of 36 [+] Feedback CYONS2000 Orientation of Axes Figure 14 describes the relationship between the package and the x/y axes when using the API provided by Cypress's PSoC Designer software. Note that there is a 90-degree rotation between the orientation below and the orientation described in the register section of the technical reference manual. If PSoC Designer is not used, the application firmware should read and invert the Y count register for X data, and read the X count register for Y data. Figure 14. Sensor Orientation when using Cypress PSoC Designer Software PCB Mounting Height and Thickness Figure 15 shows the recommended thickness and mounting height of the PCB above the tracking surface. Figure 15. PCB Height and Thickness Document Number: 001-44044 Rev. *G Page 27 of 36 [+] Feedback CYONS2000 Thermal Impedances Package 42 PQFN [15] Typical JA[14] 24 C/W Solder Reflow Peak Temperature Following is the minimum solder reflow peak temperature to achieve good solderability. Package 42 PQFN Minimum Peak Temperature[16] 240 C Maximum Peak Temperature 260 C Notes 14. TJ = TA + Power x JA. 15. To achieve the thermal impedance specified for the QFN package, the center thermal pad must be soldered to the PCB ground plane. 16. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 5C with Sn-Pb or 245 5C with Sn-Ag-Cu paste. Refer to the solder manufacturer specifications. For a recommended soldering profile, refer to Application Note 49035, Manufacturing Considerations for the OvationONSTM Laser Navigation System-on-Chip. Document Number: 001-44044 Rev. *G Page 28 of 36 [+] Feedback CYONS2000 Laser Safety Considerations The CYONS2000 laser navigation SoC and the CYONSLENS2000 lens are designed and tested to enable manufacturers to achieve eye-safety certification with minimal effort. This section provides guidelines for complying with the Class 1 emission requirements of IEC/EN 60825-1. When installed and operated in accordance with all requirements in this datasheet, the kit consisting of the CYONS2000 laser navigation SoC and CYONSLENS2000 satisfies CDRH 21 CFR 1040 per Laser Notice 50 and IEC/EN 60825-1 Class 1. Laser Output Power Test Procedure To verify the laser output level, follow the steps shown in the "VCSEL Power Calibration and Verification" section of the technical reference manual. Registration Assistance The mouse or end-product supplier is responsible for certifying the end-use product with respect to the drive voltage, manuals and labels, and operating temperature specifications. Additionally, for products sold in the US, a CDRH report must be filed for each model produced, and test and inspection of the product's characteristics as they relate to laser safety and the CDRH requirements must be performed. When filing a report with the CDRH, the supplier can refer to the product report filed by Cypress for the CYONS2xxx family of products. The Cypress report is based on the previously-noted limits for voltage and temperature, and describes how the sensor design includes consideration of drive circuit failures, laser output variation with temperature, drive circuit variation with temperature and voltage, polarization sensitivity of molded optics, and measurement uncertainties. Cypress can provide assistance to customers who want to obtain registration. Supporting documentation, including a verification test procedure to demonstrate end-product compliance with IEC and CDRH requirements is available. Laser Output Power The CYONS2000 sensor package contains an integrated VCSEL and drive circuitry. Before shipping, Cypress adjusts the laser output power to eye-safe levels, taking into account specified variations in supply voltage, temperature, lens transmission, and VCSEL polarization, and factors such as VCSEL aging and test equipment accuracy. The output remains within eye-safe limits under reasonably foreseeable single-faults, as required by the IEC standard. From the perspective of a manufacturer, laser emission remains within the Class 1 limit, as defined in IEC 60825-1, Edition 2, 2007, provided the following requirements are met. The supply voltage applied to pins DVDD and AVDD of the SoC must be in the range of 2.7 to 3.6 V. The operating temperature must be between 5 and 45 C. The laser output power must not be increased by any means, including but not limited to firmware, hardware, or mechanical modifications to the sensor or lens. The mechanical housing must be designed such that the CYONSLENS2000 cannot be removed by the user. The device firmware must initialize the VCSEL driver as described in the "VCSEL Driver" chapter of the OvationONS II technical reference manual, or by using the NAV or LaserNAV User Modules in Cypress's PSoC Designer software. The manufacturer must ensure that these conditions are always met and demonstrate end-product compliance to the appropriate regulatory standards. Document Number: 001-44044 Rev. *G Page 29 of 36 [+] Feedback CYONS2000 Development Tool Selection This section presents the development tools available for all current PSoC device families including the CYONS2000. iMAGEcraft C compiler (registration required) ISSP cable USB 2.0 cable and Blue Cat-5 cable Two CY8C29466-24PXI 28-PDIP chip samples Software PSoC Designer At the core of the PSoC development software suite is PSoC Designer, used to generate PSoC firmware applications. PSoC Designer is available free of charge at http://www.cypress.com/psocdesigner and includes a free C compiler with version Service Pack 4.5 or later. PSoC Programmer Flexible enough to be used on the bench in development, yet suitable for factory programming, PSoC Programmer works either as a standalone programming application or operates directly from PSoC Designer. PSoC Programmer software is compatible with both PSoC ICE-Cube In-Circuit Emulator and PSoC MiniProg. PSoC programmer is available free of charge at http://www.cypress.com/psocprogrammer. Evaluation Tools You can purchase the evaluation tools from the Cypress Online Store. CY3210-MiniProg1 The CY3210-MiniProg1 kit enables a user to program PSoC devices using the MiniProg1 programming unit. The MiniProg is a small, compact prototyping programmer that connects to the PC through a provided USB 2.0 cable. The kit includes: MiniProg programming unit MiniEval socket programming and evaluation board 28-pin CY8C29466-24PXI PDIP PSoC device sample 28-pin CY8C27443-24PXI PDIP PSoC device sample PSoC Designer software CD Getting Started guide USB 2.0 cable Mouse Design Kits Two kits featuring the OvationONS II family of products are available. The reference design kit provides a complete hardware, firmware, and software solution, ready for production. The demonstration kit provides tested hardware and firmware that demonstrate the capabilities of the OvationONS II device. CY4631 Wired Mouse reference design kit Wireless Mouse demonstration kit CY3210-PSoCEval1 The CY3210-PSoCEval1 kit features an evaluation board and the MiniProg1 programming unit. The evaluation board includes an LCD module, potentiometer, LEDs, and plenty of breadboarding space to meet all your evaluation needs. The kit includes: Development Kits You can purchase the development kits from the Cypress Online Store. CY3215-DK Basic Development Kit The CY3215-DK kit enables prototyping and development with PSoC Designer. This kit supports in-circuit emulation and the software interface enables users to run, halt, and single step the processor and view the content of specific memory locations. Advanced emulation features are also supported through PSoC Designer. The kit includes: Evaluation board with LCD module MiniProg programming unit 28-pin CY8C29466-24PXI PDIP PSoC device sample (2) PSoC Designer software CD Getting Started guide USB 2.0 cable PSoC Designer software CD ICE-Cube In-Circuit Emulator ICE Flex-Pod for the CY8C29x66 family Cat-5 adapter Mini-Eval programming board 110 ~ 240 V power supply, Euro-Plug adapter Document Number: 001-44044 Rev. *G Page 30 of 36 [+] Feedback CYONS2000 CY3214-PSoCEvalUSB The CY3214-PSoCEvalUSB evaluation kit features a development board for the CY8C24794-24LFXI PSoC device. Special features of the board include both USB and capacitive sensing development and debugging support. This evaluation board also includes a LCD module, potentiometer, LEDs, an enunciator and plenty of breadboarding space to meet all of your evaluation needs. The kit includes: CY3207ISSP In-System Serial Programmer (ISSP) The CY3207ISSP is a production programmer. It includes protection circuitry and an industrial case that is more robust than the MiniProg in a production-programming environment. Note CY3207ISSP needs special software and is not compatible with PSoC Programmer. The kit includes: PSoCEvalUSB board LCD module MIniProg programming unit Mini USB cable PSoC Designer and example projects CD Getting Started guide Wire pack CY3207 programmer unit PSoC ISSP software CD 110 ~ 240 V power supply, Euro-Plug adapter USB 2.0 cable Third Party Tools Several tools have been specially designed by third-party vendors to accompany PSoC devices during development and production. Specific details for each of these tools are found at http://www.cypress.com. Device Programmers You can purchase the device programmers from the Cypress Online Store. CY3216 Modular Programmer The CY3216 Modular Programmer kit features a modular programmer and the MiniProg1 programming unit. The modular programmer includes three programming module cards and supports multiple Cypress products. The kit includes: Modular programmer base Three programming module cards MiniProg programming unit PSoC Designer software CD Getting Started guide USB 2.0 cable Document Number: 001-44044 Rev. *G Page 31 of 36 [+] Feedback CYONS2000 Package Diagrams Figure 16. QFN Package SIDE VIEW TOP VIEW BOTTOM VIEW 0.50-0.60 [2X] 0.05 MAX 1.40 MAX 8.300 SQ SEE DETAIL - B SEE DETAIL - A ~ ~ 2 Pin 1 0.20 MAX (PIN1 ID) 0.50-0.60 SEATING PLANE +0.05 0.42-0.00 X 45 [4X] +0.025 [2X] O0.64 -0.025 THRU DETAIL - A SCALE: 2/1 NOTES: 1. ALL DIMENSIONS ARE IN MM , [ MIN/MAX] 2. REFRENCE JEDEC # MO-220 +0.025 O0.64 -0.025 THRU 3. PKG WEIGHT: 0.2 grams 4. APERTURE MOLD CAVITY I .D. DETAIL - B SCALE: 2/1 NON-SOLDERABLE PADS 001-44934 *C Document Number: 001-44044 Rev. *G Page 32 of 36 [+] Feedback CYONS2000 Figure 17. Lens 001-44677 *B Document Number: 001-44044 Rev. *G Page 33 of 36 [+] Feedback CYONS2000 Ordering Information The CYONS2000 and CYONSLENS2000 are sold separately. When placing orders, order both part numbers. Part Number CYONS2000-LBXC CYONSLENS2000-C 42 pin PQFN Lens - 4 mm height Package Application Desktop wired Molded optic Ordering Code Definition CY ONS XXXX - XXX C Temperature range: Commercial 42- pin PQFN package Wired laser navigation system-on-chip Optical navigation sensor Company ID : CY = Cypress Document Number: 001-44044 Rev. *G Page 34 of 36 [+] Feedback CYONS2000 Document Conventions Acronyms Used Table 20 lists the acronyms used in this document. Numeric Naming Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase `h' (for example, `14h' or `3Ah'). Hexadecimal numbers may also be represented by a `0x' prefix, the C coding convention. Binary numbers have an appended lowercase `b' (for example, `01010100b' or `01000011b'). Numbers not indicated by an `h', `b', or `0x' are decimal. Units of Measure A units of measure table in Table 21 lists the abbreviations used to measure the devices. Table 20. Acronyms Acronym AC ADC API CDRH CPI CPU DAC DC DSP ESD GND GPIO HEX High-Z I2C ICE IDAC IDE IEC ILO IMO I/O JEDEC LCD Alternating Current Analog to Digital Converter Application Programming Interface Center for Devices and Radiological Health Counts per Inch Central Processing Unit Digital to Analog Converter Direct Current Digital Signal Processor Electrostatic Discharge Ground General Purpose I/O Hexadecimal High Impedance Inter-Integrated Circuit (bus) In-circuit Emulator DAC-Controlled Current Source Integrated Development Environment International Electrotechnical Commission Internal Low Speed Oscillator Internal Main Oscillator Input/Output Joint Electron Devices Engineering Council Liquid Crystal Display Description Acronym LDO LED LPC LSb LVD M8C MCU MIPS MSb MUX PC, PCB PDIP PGA POR PQFN PSoC PSRR PWM QFN SoC SPI SRAM USB VCSEL Low Drop Out (regulator) Light Emitting Diode Low Power Comparator Least-significant Bit Low Voltage Detect Cypress' 8-bit CPU Core Microcontroller Unit Description Million Instructions per Second Most-significant Bit Multiplexer Printed Circuit, Printed Circuit Board Plastic Dual In-Line Package Programmable Gain Amplifier Power On Reset Plastic Quad Flat No-Leads (package) Programmable System-on-Chip Power Supply Rejection Ratio Pulse Width Modulator Quad Flat No-Leads (package) System on Chip Serial Peripheral Interface (bus) Static Random Access Memory Universal Serial Bus Vertical Cavity Surface Emitting Laser Table 21. Units of Measure Symbol C g KB in/s kHz k kV MHz A F H s degree Celsius acceleration of gravity 1024 bytes inches per second kilohertz kilohm kilovolt megahertz microampere microfarad microhenry microsecond Unit of Measure V Symbol microvolts milliampere millisecond millivolt nanohenry nanometer nanosecond ohm picofarad peak-to-peak volt watt mA ms mV nH nm ns pF pp V W Unit of Measure Document Number: 001-44044 Rev. *G Page 35 of 36 [+] Feedback CYONS2000 Document History Page Document Title: CYONS2000 OvationONSTM II Wired Laser Navigation System-on-Chip Document Number: 001-44044 Orig. of Submission Revision ECN Description of Change Change Date ** 2261927 FJZ See ECN New datasheet. *A 2580125 FJZ/PYRS 10/07/08 Extensive Updates *B 2769396 FJZ/AESA 25/09/09 Updated Getting Started and Development Tools sections. Updated thermal impedance, wireless kit part number, Flash specs, storage temperature, I2C footnote, pin table, and c compiler information. *C 2889331 FJZ 03/09/10 Added Table of Contents. Updated package diagram and sales links. *D 2903558 FJZ 04/20/10 Update LVD, USB, SPI Master and SPI Slave specs. Numerous minor updates for improved clarity and consistency. *E 2936335 MMCY 05/24/2010 Updated content to match the new template and style guide. No technical updates. *F 3092209 FJZ 11/22/2010 Corrected error in Pin Description. Removed invalid reference to application note in Registration Assistance. *G 3126503 FJZ 01/03/2011 Updated Figure 17. Changed posting to external web Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 (c) Cypress Semiconductor Corporation, 2008-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-44044 Rev. *G Revised January 3, 2011 Page 36 of 36 OvationONSTM, OptiCheckTM, and PSoC DesignerTM are trademarks and PSoC and CapSense are registered trademarks of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective corporations. [+] Feedback |
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